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DATA SHEET
MOS INTEGRATED CIRCUIT
PD161643
176-OUTPUT TFT-LCD GATE DRIVER
DESCRIPTION
The PD161643 is a TFT-LCD gate driver. Because this gate driver has a level shift circuit for logic input, it can output a high gate scanning voltage in response to a CMOS-level input.
FEATURES
* High-withstanding-voltage output (VT-VEE = 42 V MAX.) * 3.0 V CMOS level input * Number of output: 176
ORDERING INFORMATION
Part number 5 Package Chip
PD161643P
Remark
Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S15796EJ1V0DS00 (1st edition) Date Published February 2003 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
2001
PD161643
1. BLOCK DIAGRAM
R,/L
CLK
STVSEL STVR
SR1 SR2 SR87 SR88 SR89 SR90 SR175 SR176
STVL
MPX
OE1SEL OE1 OE2SEL OE2
VEE VSS VCC1 VT PVSS PVCC1 VB
Level Shifter
O1
O2
O87
O88
O89
O90
O175
O176
Remark
/xxx indicates active low signal.
2
Data Sheet S15796EJ1V0DS
PD161643
2. PIN CONFIGURATION (PAD LAYOUT)
Chip size: 2.3 x 7.05 mm
2 2
Bump size: INPUT/LEFT/RIGHT (include INPUT/OUTPUT/RIGHT side DUMMY): 49 x 85 m OUTPUT (include OUTPUT side DUMMY): 35 x 94 m
No.94
Alignment mark 1
2
No.95 No.96
No.93
Face Up
Y
X (0, 0)
No.1
Alignment mark 1
No.283
Alignment mark 2
No.285
No.284
Alignment mark 1
Alignment mark 2
30 m 30 m 30 m 30 m 30 m 30 m
10 m 10 m 10 m 10 m 10 m 10 m
Data Sheet S15796EJ1V0DS
3
PD161643
Table 2-1. Pad Layout (1/4) -
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Gate Inputs 70 m pitch Pad Name X [mm] Alignment Mark1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY PVCC1 OE1SEL OE1SEL PVSS OE2SEL OE2SEL PVCC1 STVSEL STVSEL PVSS R,/L R,/L PVCC1 DUMMY DUMMY VT VT VT VT VT DUMMY DUMMY VCC1 VCC1 VCC1 VCC1 VCC1 DUMMY DUMMY VSS VSS VSS VSS VSS DUMMY DUMMY VEE VEE -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 Y [mm] -3.3745 -3.2200 -3.1500 -3.0800 -3.0100 -2.9400 -2.8700 -2.8000 -2.7300 -2.6600 -2.5900 -2.5200 -2.4500 -2.3800 -2.3100 -2.2400 -2.1700 -2.1000 -2.0300 -1.9600 -1.8900 -1.8200 -1.7500 -1.6800 -1.6100 -1.5400 -1.4700 -1.4000 -1.3300 -1.2600 -1.1900 -1.1200 -1.0500 -0.9800 -0.9100 -0.8400 -0.7700 -0.7000 -0.6300 -0.5600 -0.4900 -0.4200 -0.3500 -0.2800 -0.2100 -0.1400 -0.0700 0.0000 0.0700 0.1400 0.2100 0.2800 0.3500 0.4200 0.4900 0.5600 0.6300 0.7000 0.7700 0.8400 0.9100 0.9800 1.0500 1.1200 1.1900 1.2600 Pad No. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Gate Inputs 70 m pitch Pad Name X [mm] VEE VEE VEE DUMMY DUMMY VB VB VB VB VB DUMMY DUMMY STVR STVR DUMMY STVL STVL DUMMY CLK CLK DUMMY OE1 OE1 DUMMY OE2 OE2 DUMMY DUMMY Alignment Mark1 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 -0.9995 Y [mm] 1.3300 1.4000 1.4700 1.5400 1.6100 1.6800 1.7500 1.8200 1.8900 1.9600 2.0300 2.1000 2.1700 2.2400 2.3100 2.3800 2.4500 2.5200 2.5900 2.6600 2.7300 2.8000 2.8700 2.9400 3.0100 3.0800 3.1500 3.2200 3.3745
4
Data Sheet S15796EJ1V0DS
PD161643
Table 2-1. Pad Layout (2/4) -
Pad No. 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Gate Outputs 35 m pitch Pad Name X [mm] DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY O176 O175 O174 O173 O172 O171 O170 O169 O168 O167 O166 O165 O164 O163 O162 O161 O160 O159 O158 O157 O156 O155 O154 O153 O152 O151 O150 O149 O148 O147 O146 O145 O144 O143 O142 O141 O140 O139 O138 O137 O136 O135 O134 O133 O132 O131 O130 O129 O128 O127 O126 O125 O124 O123 O122 O121 O120 O119 O118 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 Y [mm] 3.2725 3.2375 3.2025 3.1675 3.1325 3.0975 3.0625 3.0275 2.9925 2.9575 2.9225 2.8875 2.8525 2.8175 2.7825 2.7475 2.7125 2.6775 2.6425 2.6075 2.5725 2.5375 2.5025 2.4675 2.4325 2.3975 2.3625 2.3275 2.2925 2.2575 2.2225 2.1875 2.1525 2.1175 2.0825 2.0475 2.0125 1.9775 1.9425 1.9075 1.8725 1.8375 1.8025 1.7675 1.7325 1.6975 1.6625 1.6275 1.5925 1.5575 1.5225 1.4875 1.4525 1.4175 1.3825 1.3475 1.3125 1.2775 1.2425 1.2075 1.1725 1.1375 1.1025 1.0675 1.0325 Pad No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 Gate Outputs 35 m pitch Pad Name X [mm] O117 O116 O115 O114 O113 O112 O111 O110 O109 O108 O107 O106 O105 O104 O103 O102 O101 O100 O99 O98 O97 O96 O95 O94 O93 O92 O91 O90 O89 O88 O87 O86 O85 O84 O83 O82 O81 O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 Y [mm] 0.9975 0.9625 0.9275 0.8925 0.8575 0.8225 0.7875 0.7525 0.7175 0.6825 0.6475 0.6125 0.5775 0.5425 0.5075 0.4725 0.4375 0.4025 0.3675 0.3325 0.2975 0.2625 0.2275 0.1925 0.1575 0.1225 0.0875 0.0525 0.0175 -0.0175 -0.0525 -0.0875 -0.1225 -0.1575 -0.1925 -0.2275 -0.2625 -0.2975 -0.3325 -0.3675 -0.4025 -0.4375 -0.4725 -0.5075 -0.5425 -0.5775 -0.6125 -0.6475 -0.6825 -0.7175 -0.7525 -0.7875 -0.8225 -0.8575 -0.8925 -0.9275 -0.9625 -0.9975 -1.0325 -1.0675 -1.1025 -1.1375 -1.1725 -1.2075 -1.2425
Data Sheet S15796EJ1V0DS
5
PD161643
Table 2-1. Pad Layout (3/4) -
Gate Outputs 35 m pitch Pad Name X [mm] O52 O51 O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950 0.8650 0.9950
Pad No. 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283
Y [mm] -1.2775 -1.3125 -1.3475 -1.3825 -1.4175 -1.4525 -1.4875 -1.5225 -1.5575 -1.5925 -1.6275 -1.6625 -1.6975 -1.7325 -1.7675 -1.8025 -1.8375 -1.8725 -1.9075 -1.9425 -1.9775 -2.0125 -2.0475 -2.0825 -2.1175 -2.1525 -2.1875 -2.2225 -2.2575 -2.2925 -2.3275 -2.3625 -2.3975 -2.4325 -2.4675 -2.5025 -2.5375 -2.5725 -2.6075 -2.6425 -2.6775 -2.7125 -2.7475 -2.7825 -2.8175 -2.8525 -2.8875 -2.9225 -2.9575 -2.9925 -3.0275 -3.0625 -3.0975 -3.1325 -3.1675 -3.2025 -3.2375 -3.2725
6
Data Sheet S15796EJ1V0DS
PD161643
Table 2-1. Pad Layout (4/4) -
Pad No. 94 95 Gate Left 600 m pitch Pad Name X [mm] DUMMY DUMMY -0.3000 0.3000 Y [mm] 3.3925 3.3925 Pad No. 284 285 Gate Right 600 m pitch Pad Name X [mm] DUMMY DUMMY 0.3000 -0.3000 Y [mm] -3.3925 -3.3925
Pad No. -
Pad Name Alignment Mark2
X [mm] 0.9950
Y [mm] -3.3925
Data Sheet S15796EJ1V0DS
7
PD161643
3. PIN FUNCTIONS
(1/2)
Symbol O1 to O176 Pin Name Driver output Pad No. 277 to 102 I/O Output Function Scan signal output pins that drive the gate electrode of a TFTLCD. The status of each output pin changes in synchronization with the rising edge of shift clock. The output voltage of the driver is VT-VB. STVR, STVL Start pulse input/output 78, 79, 81, 82 I/O Input/output pin of the internal shift register. Read of start pulse signal is set at rising (or falling) edge of shift clock, and outputs a scanning signal from a driver output pin. In addition, the effective level of a STVR/STVL pin is determined by setup of STVSEL pin. Moreover, an input/output level is VCC1VSS (logic level). STVSEL = L: Start pulse is set to low level by the 176th falling edge of shift clock, and is set to a high level by the 177th falling edge. STVSEL Start pulse input effective level selection 35, 36 Input The effective level of the start pulse signal inputted into STVR/STVL is selected. STVSEL = L: Low level STVSEL = H: High level CLK Shift clock input 84, 85 Input Shift clock input for the internal shift register. The contents of internal shift register is shifted at the rising edge of CLK. Connect to GCLK pin of source driver. R,/L Shift direction switching input OE1 Enable input 87, 88 Input 38, 39 Input Shift direction switching input pin of the internal shift register. R,/L = H (right shift): STVR O1 O2 *** O175 O176 STVL R,/L = L (left shift): STVL O176 O175 *** O2 O1 STVR Input of the level selected by OE1SEL fixes a driver output to a low level (input of a low level fixes driver output to low level at the time of OE1SEL = L). However, shift register is not cleared. Moreover, output enable operation is asynchronous on a clock. Connect with GOE1 pin of sauce driver. OE1SEL OE1 effective level selection OE2 Enable input 90, 91 Input 29, 30 Input This pin selects effective level of OE1 pin. OE1SEL = L: Low level OE1SEL = H: High level Input of the level selected by OE2SEL fixes a driver output to a high level (input of a low level fixes driver output to high level at the time of OE2SEL = L). However, shift register is not cleared. Moreover, output enable operation is asynchronous on a clock. Connect with GOE2 pin of sauce driver. OE2SEL OE2 effective level selection 32, 33 Input This pin selects effective level of OE2 pin. OE2SEL = L: Low level OE2SEL = H: High level
8
Data Sheet S15796EJ1V0DS
PD161643
(2/2)
Symbol VT VEE VB VCC1 VSS PVCC1 PVSS Name Positive power supply for driver Negative power supply for logic Negative power supply for driver Positive power supply for logic Ground Pull-up power supply Pull-down power supply 31, 37 - 57 to 61 28, 34, 40 - - Connect to the system ground. Pull-up power supply for mode setting pins (R,/L, STVSEL, OE1SEL, OE2SEL). Pull-down power supply for mode setting pins (R,/L, STVSEL, OE1SEL, OE2SEL). 50 to 54 - 71 to 75 - Negative power supply for output buffer. Negative power supply for Liquid crystal. Positive power supply for logic circuit. 64 to 68 - Pad No. 43 to 47 I/O - Function Positive power supply for level shifter and output buffer. Positive power supply for Liquid crystal. Negative power supply for level shifter.
4. MODE DESCRIPTION
Output Mode Selection
R,/L H L Input Output STVR STVL Output Input Scan Direction 1 176 176 1
Remark H: VCC1, L: VSS
Data Sheet S15796EJ1V0DS
9
PD161643
5. TIMING CHART
The timing chart in each condition is shown as follows.
R,/L = H, STVSEL = L, OE1SEL = L, OE2SEL = L 1 CLK OE1 OE2 STVR O1 O2 O3 2 3 4 176 177 178 179 180 181
O176 STVL (O1) (O2) (O3)
R,/L = L, STVSEL = H, OE1SEL = H, OE2SEL = H 1 CLK OE1 OE2 STVL O176 O175 O174 2 3 4 176 177 178 179 180 181
O1 STVR (O176 ) (O175 ) (O174 )
10
Data Sheet S15796EJ1V0DS
PD161643
R,/L = H, STVSEL = H, OE1SEL = L, OE2SEL = H 1 CLK OE1 OE2 STVR O1 O2 O3 2 3 4 176 177 178 179 180 181
O176 STVL (O1) (O2) (O3)
R,/L = L, STVSEL = H, OE1SEL = H, OE2SEL = L 1 CLK OE1 OE2 STVL O176 O175 O174 2 3 4 176 177 178 179 180 181
O1 STVR (O176 ) (O175 ) (O174 )
Data Sheet S15796EJ1V0DS
11
PD161643
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage Input Voltage
Note
Symbol VT VCC1 VT-VEE VEE VB VI TA Tstg
Rating -0.5 to +30 -0.5 to +6.5 -0.5 to +45 -25 to +0.5 VEE - 0.5 to +0.5 -0.5 to VCC1 + 0.5 -40 to +85 -55 to +150
Unit V V V V V V C C
Operating Ambient Temperature Storage Temperature
Note R,/L, CLK, STVR, STVL, OE1, OE2, STVSEL, OE1SEL, OE2SEL Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = -40 to +85C, VSS = 0 V)
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage Input Voltage
Note
Symbol VT VEE VB VT-VEE VCC1 VI
MIN. 10 -20 VEE 20 2.5 0
TYP. 15 -15 -15 30 3.0
MAX. 25 -10 -6.5 42 3.6 VCC1
Unit V V V V V V
Note R,/L, CLK, STVR, STVL, OE1, OE2, STVSEL, OE1SEL, OE2SEL
12
Data Sheet S15796EJ1V0DS
PD161643
Electrical Characteristics (TA = -40 to +85C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = VB = -15 V, VSS = 0 V)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Output ON Resistance Input Current Dynamic Current 1 Dynamic Current 2 Dynamic Current 3 Static Current
Note
Symbol VIH1 VIL1 VOH VOL RON1 RON2 II1 ICC1 IT IEE ISS
Condition R,/L, CLK, STVR, STVL, OE1, OE2, STVSEL, OE1SEL, OE2SEL STVR, STVL, IOH = -40 A STVR, STVL, IOH = +40 A O1 to O176, VOUT = VT - 0.5 V O1 to O176, VOUT = VEE + 0.5 V Logic input pin VCC1, Note VT, Note VEE, Note VCC1, VT in stand-by mode
MIN. 0.8 VCC1 0 VCC1 - 0.4 0
TYP.
MAX. VCC1 0.2 VCC1 VCC1 0.4
Unit V V V V k k
5.0 5.0
7.5 7.5 1.0 200 100 100 10
A A A A A
Note fCLK = 20 kHz, frame frequency = 60 Hz, output no load Switching Characteristics (TA = -40 to +85C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = VB = -15 V, VSS = 0 V)
Parameter Cascade Output Delay Time Symbol tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tTLH tTHL CI fCLK TA = 25C When connected in cascade 20 CL = 20 pF, CLK STVL (STVR) CL = 50 pF, CLK On CL = 50 pF, OE1 On CL = 50 pF, OE2 On CL = 50 pF Condition MIN. TYP. MAX. 800 800 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 15 100 Unit ns ns
5 5 5 5
Driver Output Delay Time 1 Driver Output Delay Time2 Driver Output Delay Time 3 Output Rise Time Output Fall Time Input Capacitance Clock Frequency
s s s s s s s s
pF kHz
Timing Requirement (TA = -40 to +85C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = VB = -15 V, VSS = 0 V)
Parameter Clock Pulse High Period Clock Pulse Low Period Enable Pulse High Period Data Setup Time Data Hold Time Symbol PWCLK(H) PWCLK(L) PWOE tSETUP tHOLD OE1, OE2 STVR (STVL) CLK CLK STVR (STVL) Condition MIN. 500 500 1 200 200 TYP. MAX. Unit ns ns
s
ns ns
Remark
The rise and fall times of logic input must be tr = tf = 20 ns (10 to 90%)
Data Sheet S15796EJ1V0DS
13
PD161643
5 Switching Characteristics Waveform (R,/L = H, STVSEL = L, OE1SEL = L, OE2SEL = L)
1/fCLK PWCLK(H) PWCLK(L) VCC1 CLK 50% 50% 50% 50% VSS tSETUP tHOLD VCC1 STVR (STVL) 50% 50% VSS tPHL1 tPLH1 VCC1 STVL (STVR) 50% 50% VSS tPLH2 tTLH 90% On tPHL2 90% tTHL VT
( ): R,/L = L
10%
10% VB
PWOE VCC1 OE1 50% 50% VSS tPHL3 90% On 10% VB PWOE VCC1 OE2 50% 50% VSS tPLH4 tPHL4 VT 90% On 10% VB tPLH3 VT
14
Data Sheet S15796EJ1V0DS
PD161643
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S15796EJ1V0DS
15

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